A dynamic latch circuit of a semiconductor integrated circuit generally consists of a clocked inverter and an inverter, or a transfer gate and an inverter.
A first conventional dynamic latch circuits is composed of a clocked inverter and an inverter connected through a holding line to the clocked inverter. In this conventional dynamic latch circuit, when an input signal is supplied to the clocked inverter, the input signal is inverted based on the timing of a clock signal applied to the clocked inverter, so that the inverted signal is supplied on the holding line to be connected to the inverter. Thus, an output signal which is obtained by inverting the inverted signal is generated on an output line of the inverter.
This conventional dynamic latch circuit has an integrated circuit structure, such that an input line for the input signal, a clock line fore the clock signal and a part of the holding line which is an input line of the inverter are provided as a first interconnection layer on a semiconductor substrate, the other part of the holding line which is an output line of the clocked inverter and a part of the output line of the inverter are provided as a second interconnection layer which is insulated from the first interconnection layer by an insulating layer, and the other part of the output line of the inverter is provided as a third interconnection layer which is insulated from the second interconnection layer by an insulating layer.
A second conventional dynamic latch circuit includes a through line in addition to the structure of the first conventional dynamic latch circuit. The through line is assumed to be formed as the third interconnection layer which is positioned above the second interconnection layer. The through line is connected with other circuits, and operates independently with the latch circuit. Therefore, interfaces of each insulating layer can be used efficiently to increase an integration degree.
According to the second conventional dynamic latch circuit, however, there is a disadvantage in that the holding line is affected by a coupling capacitance with the through line, so that a malfunction occurs by a crosstalk between the holding line and the through line.